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LTM9002 14-Bit Dual-Channel IF/ Baseband Receiver Subsystem FEATURES
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DESCRIPTION
The LTM(R)9002 is a 14-bit dual-channel IF receiver subsystem. Utilizing an integrated system in a package (SiP) technology, it includes a dual high-speed 14-bit A/D converter, matching network, anti-aliasing filter and two low noise, differential amplifiers. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) up to 300MHz. The amplifiers allow either AC- or DCcoupled input drive. Lowpass or bandpass filter networks can be implemented with various bandwidths. Contact Linear Technology regarding customization. The LTM9002 is perfect for demanding communications applications, with AC performance that includes 66dB SNR and 76dB spurious free dynamic range (SFDR). Auxiliary DACs allow gain balancing between channels. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. An optional multiplexer allows both channels to share a digital output bus. Two single-ended CLK inputs can be driven together or independently. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
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Integrated Dual 14-Bit, High-Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Up to 300MHz IF Range Lowpass and Bandpass Filter Versions Integrated Low Noise, Low Distortion Amplifiers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50, 200 or 400 Input Impedance Integrated Bypass Capacitance, No External Components Required 66dB SNR Up to 140MHz Input (LTM9002-AA) 76dB SFDR Up to 140MHz Input (LTM9002-AA) Auxiliary 12-Bit DACs for Gain Adjustment Clock Duty Cycle Stabilizer Single 3V to 3.3V Supply Low Power: 1.3W (665mW/ch.) Shutdown and Nap Modes 15mm x 11.25mm LGA Package
APPLICATIONS
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Telecommunications Direct Conversion Receivers Main and Diversity Receivers Cellular Base Stations
TYPICAL APPLICATION
Dual Channel IF Receiver
VCC = 3V VDD OVDD 0.5V TO 3.6V
64k Point FFT, fIN = 15MHz, -1dBFS, SENSE = VDD, Channel A (LTM9002-LA)
0 -10 -20 AMPLITUDE (dBFS) -30
VREF
INA+ MAIN RF LO DAC DIFFERENTIAL AMPLIFIERS DAC INB+ DIVERSITY RF LO
9002 TA01
SAW
INA-
FILTER
14-BIT 125Msps ADC
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 FREQUENCY (MHz) 30
9002 TA01b
CLKOUT ADC CLK SPI MUX OF
SAW
INB-
FILTER
14-BIT 125Msps ADC
OGND
GND
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LTM9002 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
SENSEB SENSEA ALL OTHERS = GND
J
Supply Voltage (VCC) ................................ -0.3V to 3.6V Supply Voltage (VDD, OVDD)......................... -0.3V to 4V Digital Output Ground Voltage (OGND) ........ -0.3V to 1V Input Current (IN+, IN-)........................................10mA DAC Digital Input Voltage (CS/LD, SDI, SCK) ................................... -0.3V to 6V Digital Input Voltage (Except AMPSHDN) ................. -0.3V to (VDD + 0.3V) Digital Input Voltage (AMPSHDN)..............................-0.3V to (VCC + 0.3V) Digital Output Voltage ................-0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9002C................................................ 0C to 70C LTM9002I.............................................-40C to 85C Storage Temperature Range...................-65C to 125C
INA+ INA- VCC
H G F E D
OVDD
OGND VDD
OGND
INB- INB+
C B A 1 2 3 4 5 6 7 8 9 10 11 12
OVDD
CLKA CLKB
CONTROL
DATA
LGA PACKAGE 108-LEAD (15mm x 11.25mm x 2.32mm) TJMAX = 125C, JA = 19C/W, JCTOP = 16C/W, JCBOT = 6C/W JA DERIVED FROM 101.5mm x 114.5mm PCB WITH 4 LAYERS WEIGHT = 0.935g
ORDER INFORMATION
LEAD FREE FINISH LTM9002CV-AA#PBF LTM9002CV-LA#PBF LTM9002IV-AA#PBF LTM9002IV-LA#PBF TRAY LTM9002CV-AA#PBF LTM9002CV-LA#PBF LTM9002IV-AA#PBF LTM9002IV-LA#PBF PART MARKING* LTM9002VAA LTM9002VLA LTM9002VAA LTM9002VLA PACKAGE DESCRIPTION 108-Lead (15mm x 11.25mm x 2.3mm) LGA 108-Lead (15mm x 11.25mm x 2.3mm) LGA 108-Lead (15mm x 11.25mm x 2.3mm) LGA 108-Lead (15mm x 11.25mm x 2.3mm) LGA TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTM9002
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted. (Note 3)
SYMBOL GDIFF PARAMETER Gain CONDITIONS DC, LTM9002-AA fIN = 140MHz Channel A, DC (LTM9002-LA) fIN = 15MHz Channel B, DC (LTM9002-LA) fIN = 15MHz GTEMP VIN Gain Temperature Drift Gain Matching Input Voltage Range for -1dBFS VIN = MAX, (Note 3) External Reference Both Channels, fIN = 140MHz (LTM9002-AA) Channel A, fIN = 15MHz (LTM9002-LA) Channel B, fIN = 15MHz (LTM9002-LA) VINCM RINDIFF Input Common Mode Voltage Range Differential Input Impedance Both Channels (LTM9002-AA) Channel A (LTM9002-LA) Channel B (LTM9002-LA) CINDIFF VOS Differential Input Capacitance Offset Error (Note 5) Offset Matching Offset Drift CMRR ISENSE IMODE tAP tJITTER Common Mode Rejection Ratio SENSE Input Leakage MODE Input Leakage Sample and Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter 0V < SENSE < 1V 0V < MODE < VDD
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ELECTRICAL CHARACTERISTICS
MIN 25 19.4 7.5
TYP 26 25 20 19 8 7 1.5 5 100 200 800
MAX 27 20.6 8.5
UNITS dB dB dB dB dB dB mdB/C mdB mVP-P mVP-P mVP-P
1 50 200 400 1
l
1.5
V pF
Includes Parasitic Including Amplifier and ADC Including Amplifier and ADC -3 -3 -5
0.3 0.3 10 50
5
mV mV V/C dB
3 3 0 0.2
A A ns psRMS
CONVERTER CHARACTERISTICS
SYMBOL ADC Characteristics Resolution (No Missing Codes) INL DNL Integral Linearity Error (Note 4) Differential Linearity Error PARAMETER
The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS LTM9002-AA LTM9002-LA LTM9002-AA LTM9002-LA LTM9002-AA LTM9002-LA
l l l l
MIN 14 12
TYP
MAX
UNITS Bits Bits
1.5 0.3 -1 -1 0.6 0.2 1 1
LSB LSB LSB LSB
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LTM9002 DYNAMIC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Input = -1dBFS. (Note 3)
CONDITIONS 70MHz Input (Both Channels), LTM9002-AA 140MHz Input (Both Channels), LTM9002-AA 15MHz Input (Channel A), LTM9002-LA 15MHz Input (Channel B), LTM9002-LA
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MIN 61.5 67.7 68.5 67.5 75 72.7 74.2 78.8 79.8 60.7 67.1 67.9
TYP 66 66 69.9 71.1 82 76 86.2 85.5 90 90 88.5 90.7 66 66 69.7 70.8 77 73 77 -110 -110
MAX
UNITS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBc dBc dBc dB dB
SFDR
Spurious Free Dynamic Range, 2nd or 3rd Harmonic
70MHz Input (Both Channels), LTM9002-AA 140MHz Input (Both Channels), LTM9002-AA 15MHz Input (Channel A), LTM9002-LA 15MHz Input (Channel B), LTM9002-LA
SFDR
Spurious Free Dynamic Range 4th or Higher
70MHz Input (Both Channels), LTM9002-AA 140MHz Input (Both Channels), LTM9002-AA 15MHz Input (Channel A), LTM9002-LA 15MHz Input (Channel B), LTM9002-LA
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
70MHz Input (Both Channels), LTM9002-AA 140MHz Input (Both Channels), LTM9002-AA 15MHz Input (Channel A), LTM9002-LA 15MHz Input (Channel B), LTM9002-LA
IMD3
Third Order Inter-Modulation Distortion; 1MHz Tone Spacing, Two Tones -7dBFS Crosstalk
70MHz Input, LTM9002-AA 140MHz Input, LTM9002-AA 15MHz Input, LTM9002-LA 140MHz Input, LTM9002-AA 15MHz Input, LTM9002-LA
AUXILIARY DAC CHARACTERISTICS
PARAMETER Resolution Monotonicity Full-Scale Range Settling Time Internal Reference 0.024% (1LSB at 12 Bits), No External Sense Capacitor CONDITIONS
The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Not applicable for LTM9002-LA) (Note 3)
MIN
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TYP
MAX
UNITS Bits Bits
12 12 1.5 83.5
V s
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL VIH VIL IIN CIN PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V VIN = 0V to VDD (Note 6)
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DIGITAL INPUTS AND OUTPUTS
MIN 2
TYP
MAX
UNITS V
Logic Inputs (CLK, OE, ADCSHDN, MUX, CS/LD, SCK, SDI) 0.8 -10 3 10 V A pF
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LTM9002
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL VIL VIH IIL IIH Logic Outputs OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA 1.79 0.1 V V High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA 2.49 0.09 V V Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = 3V (Note 6) VOUT = 0V VOUT = 3V IO = -10A IO = -200A IO = 10A IO = 1.6mA
l l
DIGITAL INPUTS AND OUTPUTS
PARAMETER Low Level Input Voltage High Level Input Voltage Input Low Current Input High Current
CONDITIONS
l l
MIN
TYP
MAX 0.8
UNITS V V A A
Logic Inputs (AMPSHDN) 2.4 0.5 1.4 3
AMPSHDN = 0.8V AMPSHDN = 2.4V
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3 50 50 2.7 2.995 2.99 0.005 0.09 0.4
pF mA mA V V V V
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 7)
SYMBOL PARAMETER VCC VDD OVDD ICC Amplifier and Auxiliary DAC Operating Supply Range ADC Analog Supply Voltage Output Supply Voltage Amplifier DAC Powered Up, Both Amplifiers Enabled, LTM9002-AA Both Amplifiers Enabled, LTM9002-LA ICC(SHDN) Amplifier Shutdown Supply Current IDD(ADC) ADC Supply Current AMPSHDN = 3V, DAC Powered Down LTM9002-AA LTM9002-LA PD(SHDN) ADC Shutdown Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 3V, No CLK PD(NAP) PD(AMP) PD(ADC) ADC Nap Mode Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 0V, No CLK Amplifier Power Dissipation ADC Power Dissipation DAC Powered Up, LTM9002-AA LTM9002-LA LTM9002-AA LTM9002-LA PD(TOTAL) Total Power Dissipation fSAMPLE = MAX, LTM9002-AA fSAMPLE = MAX, LTM9002-LA
l l l l
POWER REQUIREMENTS
CONDITIONS
l l l l l
MIN 2.85 2.85 0.5
TYP 3.0 3.0 3.0 180 90 0.7 263 140 2 15 540 270 790 420 1329 690
MAX 3.4 3.5 3.6 207 120 313 159
UNITS V V V mA mA mA mA mA mW mW mW mW
939 477
mW mW mW mW
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LTM9002 TIMING CHARACTERISTICS
SYMBOL fS tL tH tL tH tAP tD tC tMD PARAMETER Sampling Frequency CLK Low Time CLK High Time CLK Low Time CLK High Time Absolute Aperture Delay CLK to DATA Delay CLK to CLKOUT Delay DATA to CLKOUT Skew MUX to DATA Delay DATA Access Time After OE BUS Relinquish Time Pipeline Latency SPI Interface for Aux DACs, VDD = 2.7V to 3.6V t1 t2 t3 t4 t5 t6 t7 t10 SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD CS/LD Low to SCK High CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN = ADCSHDN = 0V, unless otherwise noted. 4 4 9 9 10 7 7 7 50 ns ns ns ns ns ns ns ns MHz CL = 5pF (Note 6) CL = 5pF (Note 6) (tD - tC) (Note 6) CL = 5pF (Note 6) CL = 5pF (Note 6) (Note 6)
l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 6) (Not applicable for LTM9002-LA)
CONDITIONS LTM9002-AA LTM9002-LA Duty Cycle Stabilizer Off (Note 6), LTM9002-AA Duty Cycle Stabilizer On (Note 6), LTM9002-AA Duty Cycle Stabilizer Off (Note 6), LTM9002-AA Duty Cycle Stabilizer On (Note 6), LTM9002-AA Duty Cycle Stabilizer Off (Note 6), LTM9002-LA Duty Cycle Stabilizer On (Note 6), LTM9002-LA Duty Cycle Stabilizer Off (Note 6), LTM9002-LA Duty Cycle Stabilizer On (Note 6), LTM9002-LA
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MIN 1 1 3.8 3 3.8 3 7.3 5 7.3 5 1.4 1.4 -0.6 1.4
TYP
MAX 125 65
UNITS MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles
4 4 4 4 7.7 7.7 7.7 7.7 0 2.7 2.7 0 2.7 4.3 3.3 5
500 500 500 500 500 500 500 500 5.4 5.4 0.6 5.4 10 8.5
Note 4: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 5: Offset error is the output code resulting when the inputs are shorted together. The output code is converted to millivolts. Note 6: Guaranteed by design, not subject to test. Note 7: VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active.
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LTM9002 TIMING DIAGRAMS
Dual Digital Output Bus Timing
tAP ANALOG INPUT N N+1 tH CLKA = CLKB tD D0-D13, OF N-5 tC CLKOUT
9002 TD01
N+2 N+3
N+4 N+5
tL
N-4
N-3
N-2
N-1
N
Multiplexed Digital Output Bus Timing
tAPA ANALOG INPUT A A A+1 tAPB ANALOG INPUT B B B+1 tH CLKA = CLKB = MUX tL B+2 B+3 B+4 A+2 A+3 A+4
DA0-DA13
A-5 tD
B-5
A-4
B-4 tMD
A-3
B-3
A-2
B-2
A-1
DB0-DB13
B-5 tC
A-5
B-4
A-4
B-3
A-3
B-2
A-2
B-1
CLKOUT
9002 TD02
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LTM9002 TIMING DIAGRAMS
Auxiliary DAC Timing
t1 t2 SCK 1 t3 2 t4 3 23 t6 24 t10 SDI t5 CS/LD
9002 TD03
C3 t7
C2
C1
D1
D0
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA) Differential Non-Linearity (DNL) vs Output Code
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 12288 OUTPUT CODE 16384
9002 G01
Integral Non-Linearity (INL), Best Fit vs Output Code
4.0 3.0 2.0 SNR (dB) 1.0 0 -1.0 -2.0 -3.0 -4.0 0 4096 8192 12288 OUTPUT CODE 16384
9002 G02
SNR vs Frequency
72 71 70 69 68 67 66 65 64 63 62 1 10 100 IF FREQUENCY (MHz) 1000
9002 G03
Input Impedance vs Frequency
60 55 IMPEDANCE MAGNITUDE () 50 45 40 35 30 25 20 15 10 5 0 1 10 100 FREQUENCY (MHz) PHASE MAGNITUDE 10 9 8 IMPEDANCE PHASE (DEG) 7 6 5 4 3 2 1 0 -1 -2 1000
9002 G04
IF Frequency Response
0 -2 -4 AMPLITUDE (dBFS) -6 -8 -10 -12 -14 -16 -18 -20 1 10 100 IF FREQUENCY (MHz) 1000
9002 G05
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LTM9002 TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA) 64k Point FFT, fIN = 70MHz, -1dBFS, SENSE = VDD
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60
9002 G06
64k Point 2-Tone FFT, fIN = 70MHz and fIN = 74MHz, -7dBFS Per Tone, SENSE = VDD
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60
9002 G07
64k Point FFT, fIN = 140MHz, -1dBFS, SENSE = VDD
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60
9002 G08
64k Point 2-Tone FFT, fIN = 136MHz and fIN = 140MHz, -7dBFS Per Tone, SENSE = VDD
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60
9002 G09
(LTM9002-LA) Differential Non-Linearity (DNL) vs Output Code
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
9002 G10
Integral Non-Linearity (INL), Best Fit vs Output Code
0.5 0.4 0.3 0.2 SNR (dB) 0 1024 2048 3072 OUTPUT CODE 4096
9002 G11
SNR vs Frequency (Channel A)
72 71 70 69 68 67 66 65 64 63 62 1 10 IF FREQUENCY (MHz) 100
9002 G12
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
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LTM9002 TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Frequency (Channel B)
72 71 IMPEDANCE MAGNITUDE () 70 69 SNR (dB) 68 67 66 65 64 63 62 1 10 IF FREQUENCY (MHz) 100
9002 G13
(LTM9002-LA)
Input Impedance vs Frequency (Channel A)
200 175 150 125 100 75 50 PHASE 25 0 1 10 100 FREQUENCY (MHz) 1 0 1000
9002 G14
8 MAGNITUDE 7 IMPEDANCE PHASE (DEG) 6 5 4 3 2
Input Impedance vs Frequency (Channel B)
400 350 IMPEDANCE MAGNITUDE () 300 250 200 150 100 PHASE 50 0 1 10 100 FREQUENCY (MHz) 4 0 1000
9002 G15
IF Frequency Response
32 28 0 -2 IMPEDANCE PHASE (DEG) AMPLITUDE (dBFS) AMPLITUDE (dBFS) -4 -6 -8 -10 -12 -14 0.1 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -100 1 10 IF FREQUENCY (MHz) 100
9002 G16
64k Point FFT, fIN = 15MHz, -1dBFS, SENSE = VDD (Channel A)
MAGNITUDE
24 20 16 12 8
-120
0
5
10 15 20 25 FREQUENCY (MHz)
30
35
9002 G17
64k Point FFT, fIN = 15MHz, -1dBFS, SENSE = VDD (Channel B)
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -100 -120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35
9002 G18
64k Point 2-Tone FFT, fIN = z and fIN = 15MHz, -7dBFS Per Tone, SENSE = VDD (Channel A)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -100 -120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35
9002 G19
64k Point 2-Tone FFT, fIN = 14MHz and fIN = 15MHz, -7dBFS Per Tone, SENSE = VDD (Channel B)
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -100 -120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35
9002 G20
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LTM9002 PIN FUNCTIONS
Supply Pins GND (Pins A1-2, A5-7, B2-4, B6, C2-3, C6, D1-3, D5-7, D9-10, E5-6, E9-10, F1-2, F5-7, F9-10, G2-3, G6, H2-4, H6, J1-2, J5-7): ADC Power Ground. OGND (Pins A12, C9, G9, J12): Output Driver Ground. OVDD (Pins B12, H12): Positive supply for the ADC output drivers. The specified operating range is 0.5V to 3.6V. OVDD is internally bypassed to OGND. VCC (Pins E3, E4): Amplifier and Auxiliary DAC Power Supply. The specified operating range is 2.85V to 3.465V. The voltage on this pin provides power for the amplifier stage and auxiliary DACs only and is internally bypassed to GND. Note that LTM9002-LA does not have auxiliary DACs. VDD (Pins E7, E8): Analog 3V Supply for ADC. The specified operating range is 2.7V to 3.6V. VDD is internally bypassed to GND. Analog Inputs CLKA (Pin A3): Channel A ADC Clock Input. The input sample starts on the positive edge. CLKB (Pin A4): Channel B ADC Clock Input. The input sample starts on the positive edge. DNC1 (Pin H5): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They should be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. DNC1 connects near the channel A positive differential analog input. DNC2 (Pin G5): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They should be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. DNC2 connects near the channel A negative differential analog input. DNC3 (Pin C5): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They should be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. DNC3 connects near the channel B positive differential analog input. DNC4 (Pin B5): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They should be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. DNC4 connects near the channel B negative differential analog input. DNC5 (Pin G4): Do Not Connect. This pin is used for testing and should not be connected on the PCB. It should be soldered to an unconnected pad and should be well isolated. This is a test point for the auxiliary DAC channel A voltage output. DNC6 (Pin C4): Do Not Connect. This pin is used for testing and should not be connected on the PCB. It should be soldered to an unconnected pad and should be well isolated. This is a test point for the auxiliary DAC channel B voltage output. INA- (Pin G1): Channel A Negative (Inverting) Amplifier Input. INA+ (Pin H1): Channel A Positive (Noninverting) Amplifier Input. INB- (Pin C1): Channel B Negative (Inverting) Amplifier Input. INB+ (Pin B1): Channel B Positive (Noninverting) Amplifier Input.
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LTM9002 PIN FUNCTIONS
Control Pins ADCSHDNA (Pin G7): Channel A Shutdown Mode Selection Pin. Connecting ADCSHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting ADCSHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting ADCSHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting ADCSHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. ADCSHDNB (Pin C7): Channel B Shutdown Mode Selection Pin. Connecting ADCSHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting ADCSHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting ADCSHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting ADCSHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. AMPSHDNA (Pin E1): Power Shutdown Pin for Channel A Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with a <1mA amplifier supply current. AMPSHDNB (Pin E2): Power Shutdown Pin for Channel B Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with a <1mA amplifier supply current. MODE (Pin G8): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. VDD selects 2's complement output format and turns the clock duty cycle stabilizer off. MUX (Pin C8): Digital Output Multiplexer Control. If MUX = high, channel A comes out on DAx; channel B comes out on DBx. If MUX = low, the output busses are swapped and channel A comes out on DBx; channel B comes out on DAx. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. OEA (Pin F8): Channel A Output Enable Pin. Refer to ADCSHDNA pin function. OEB (Pin D8): Channel B Output Enable Pin. Refer to ADCSHDNB pin function. SENSEA (Pin J4): Channel A Reference Programming Pin. Connecting SENSEA to VDD selects the internal reference and the higher input range. Connecting to 1.5V selects the lower range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of VSENSEA/GAIN. See SENSE Pin Operation section. SENSEB (Pin J3): Channel B Reference Programming Pin. Connecting SENSEB to VDD selects the internal reference and the higher input range. Connecting to 1.5V selects the lower range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of VSENSEB/GAIN. See SENSE Pin Operation section. Digital Inputs (Not Connected on LTM9002-LA) CS/LD (Pin F3): Serial Interface Chip Select/Load Input for Auxiliary DAC. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 3) is executed. SCK (Pin F4): Serial Interface Clock Input for Auxiliary DAC. CMOS and TTL compatible. SDI (Pin D4): Serial Interface Data Input for Auxiliary DAC. Data is applied to SDI for transfer to the device at the rising edge of SCK. The auxiliary DAC accepts input word lengths of either 24 or 32 bits.
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12
LTM9002 PIN FUNCTIONS
Digital Outputs CLKOUT (Pin E12, LTM9002-AA): ADC Data Ready Clock Output. Latch data on the falling edge of CLKOUT. CLKOUT is derived from CLKB. Tie CLKA to CLKB for simultaneous operation. OFB (Pin E12, LTM9002-LA): Overflow/Underflow Output. High when an overflow or underflow has occurred on channel B. DA0 - DA13 (Refer to Pin Configuration Table): Channel A ADC Digital Outputs. DA13 is the MSB for LTM9002-AA; DA11 is the MSB for LTM9002-LA.
Pin Configuration (LTM9002-AA)
1 J H G F E D C B A GND INA+ INA- GND AMP SHDNA GND INB- INB+ GND 2 GND GND GND GND AMP SHDNB GND GND GND GND 3 SENSEB GND GND CS/LD VCC GND GND GND CLKA 4 SENSEA GND DNC5 SCK VCC SDI DNC6 GND CLKB 5 GND DNC1 DNC2 GND GND GND DNC3 DNC4 GND 6 GND GND GND GND GND GND GND GND GND 7 GND OF ADC SHDNA GND VDD GND ADC SHDNB DB0 GND 8 DA8 DA10 MODE OEA VDD OEB MUX DB4 DB6 9 DA5 DA12 OGND GND GND GND OGND DB2 DB9 10 DA6 DA11 DA13 GND GND GND DB1 DB3 DB8 11 DA7 DA9 DA4 DA2 DA0 DB13 DB11 DB5 DB7 12 OGND OVDD DA3 DA1 CLKOUT DB12 DB10 OVDD OGND
DB0 - DB13 (Refer to Pin Configuration Table): Channel B ADC Digital Outputs. DB13 is the MSB for LTM9002-AA; DB11 is the MSB for LTM9002-LA. OF (Pin H7, LTM9002-AA): Overflow/Underflow Output. High when an overflow or underflow has occurred on either channel A or channel B. OFA (Pin H7, LTM9002-LA): Overflow/Underflow Output. High when an overflow or underflow has occurred on channel A.
Pin Configuration (LTM9002-LA)
1 J H G F E D C B A GND INA+ INA- GND AMP SHDNA GND INB- INB+ GND 2 GND GND GND GND AMP SHDNB GND GND GND GND 3 SENSEB GND GND NC VCC GND GND GND CLKA 4 SENSEA GND DNC5 NC VCC NC DNC6 GND CLKB 5 GND DNC1 DNC2 GND GND GND DNC3 DNC4 GND 6 GND GND GND GND GND GND GND GND GND 7 GND OFA ADC SHDNA GND VDD GND ADC SHDNB NC GND 8 DA6 DA8 MODE OEA VDD OEB MUX DB2 DB4 9 DA3 DA10 OGND GND GND GND OGND DB0 DB7 10 DA4 DA9 DA11 GND GND GND NC DB1 DB6 11 DA5 DA7 DA2 DA0 NC DB11 DB9 DB3 DB5 12 OGND OVDD DA1 NC OFB DB10 DB8 OVDD OGND
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LTM9002 BLOCK DIAGRAM
Functional Block Diagram (Only One Channel is Shown)
VCC VCC
VDD
VDD OVDD
PIPELINED ADC SECTIONS IN+ ADC DRIVER IN
-
FILTER
INPUT S/H
1st
2nd
3rd
4th
5th
6th OUTPUT DRIVERS
OF*
D13 ... D0 CLKOUT* OGND
AMPSHDN
VOLTAGE REFERENCE VOLTAGE REFERENCE
SHIFT REGISTER AND ERROR CORRECTION INTERNAL REFL CLOCK SIGNALS
REFH REF BUFFER
DIFF REF AMP
DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER
CONTROL LOGIC
DAC
9001 BD
SENSE *OFA AND OFB ON LTM9002-LA
SDI SCK CS/LD
GND
CLK
MODE ADC SHDN
OE
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14
LTM9002 OPERATION
DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Aperture Delay Time The time from when CLK reaches mid supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal-to-noise ratio due to the jitter alone will be: SNRJITTER = -20log (2) * fIN * tJITTER Crosstalk The amount of signal coupled from one channel into the other. This is measured by applying a full-scale sinusoidal input on channel A, shorting the inputs of channel B and taking the ratio of the signal powers in an FFT.
( V2
2
+ V3 + V4 +KVn
2
2
2
) / V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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LTM9002 OPERATION
Description The LTM9002 is an integrated system in a package (SiP) that includes two high-speed 14-bit A/D converters, matching networks, anti-aliasing filters and two low noise, differential amplifiers with fixed gain. These amplifiers need not be the same, so that the gains and input impedances of the two channels are different. Also included is a pair of auxiliary DACs to allow for digital, full-scale adjustment of each channel. The LTM9002 is designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 300MHz. Typical applications include digitizing in-phase and quadrature channels or main and diversity channels in base station applications. The following sections describe in further detail the operation of each section. The SiP technology allows the LTM9002 to be customized and this is described in the first section. The outline of the remaining sections follows the basic functional elements as shown in Figure 1.
AUXILIARY DAC
Semi-Custom Options The Module construction affords a new level of flexibility in application-specific standard products. Standard ADC and amplifier components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9002-AA, as the first example, is configured with a dual 14-bit ADC sampling at rates up to 125Msps. The amplifier gain is 26dB with an input impedance of 50 and an input range of 100mVP-P (-16dBm). The matching network is designed to optimize the interface between the amplifier output and the ADC under these conditions. Additionally, there is a 3rd order lowpass filter with a cutoff at 170MHz. The auxiliary DACs allow adjustment of the full-scale range with 12-bit resolution. However, other options are possible through Linear Technology's semi-custom development program. Linear Technology has in place a program to deliver other speed, resolution, IF range, gain and filter configurations for nearly any specified application. These semi-custom designs are based on existing ADCs and amplifiers with an appropriately modified matching network. The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and optimized solution in the same package. For more details on the semi-custom receiver subsystem program, contact Linear Technology.
ADC SAMPLE RATE 125Msps 65Msps ADC RESOLUTION 14-Bit 12-Bit AUXILIARY DAC 12-Bit, SPI None
AMPLIFIER
ADC INPUT NETWORK
ADC
9002 F01
Figure 1. Basic Functional Elements Table 1. Semi-Custom Options
AMPLIFIER INPUT IMPEDANCE AMPLIFIER GAIN 50 26dB 200 (Channel A) 20dB (Channel A) 400 (Channel B) 8dB (Channel B) Select Combination of Options from Columns Below DC-300MHz 50 26dB DC-140MHz 200 20dB DC-70MHz 200 14dB DC-35MHz 400 8dB AMPLIFIER IF RANGE 300MHz 140MHz
FILTER 170MHz LPF 25MHz LPF
PART NUMBER LTM9002-AA LTM9002-LA
TBD
125Msps 105Msps 80Msps 65Msps 40Msps 25Msps 10Msps
14-Bit 12-Bit 10-Bit
12-Bit, I2C None
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16
LTM9002 OPERATION
Note that not all combinations in Table 1 are possible at this time and specified performance may differ significantly from existing values. AMPLIFIER OPERATION The amplifiers used in the LTM9002 are low noise and low distortion fully differential op amps/ADC drivers with operation from DC to 2GHz (-3dB bandwidth). The amplifiers are composed of fully differential amplifiers with on chip feedback and output common mode voltage control circuitry. Differential gain and input impedance are set by internal resistors in the feedback network.
Table 2. Amplifier Gain and Input Impedance
GAIN (dB) 8 14 20 26 GAIN (V/V) 2.5 5 10 20 ZIN (DIFFERENTIAL) 400 200 200 50
analog input will result in a digitized value six cycles later (see the Timing Diagram section). The CLK inputs are single-ended. The ADC has two phases of operation, determined by the state of the CLK input pins. Each pipelined stage shown in the Block Diagram contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the Block Diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. AUXILIARY DAC OPERATION The full-scale voltage span of each ADC is controlled by an auxiliary voltage output DAC connected to SENSE. Series resistance in the DAC output allows an external voltage to override the DAC. The internal reference sets both auxiliary DACs to a fullscale range to 1.5V. Programming the DAC to generate an internal voltage greater than or less than the external
9002f
The amplifiers are very flexible in terms of I/O coupling. They can be AC- or DC-coupled at the inputs. Due to the internal connection between input and output, users are advised to keep input common mode voltage between 1V and 1.7V for proper operation. If the inputs are AC-coupled, the input common mode voltage is automatically biased close to the ADC input common mode voltage and thus no external circuitry is needed for bias. The input signal can be either single-ended or differential with some difference in distortion performance. ADC INPUT NETWORK The passive network between the amplifier output stage and the ADC input stage provides a 3rd order topology that can be configured for bandpass or lowpass response and different cutoff frequencies and bandwidths. LTM9002AA, for example, implements a lowpass filter designed for 170MHz. CONVERTER OPERATION As shown in the Block Diagram, the analog-to-digital converter (ADC) is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled
17
LTM9002 OPERATION
reference adjusts the ADC span proportionately; see Adjusting the full-scale input range. Powering down the auxiliary DAC disables the ADC span trim control. When the auxiliary DAC is powered down, connect SENSE to VDD or an external reference. Power-On Reset The auxiliary DACs clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. Transfer Function The digital-to-analog transfer function is; VOUT(IDEAL) = ( k/2N ) VREF where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is 1.5V, the internal reference voltage of the ADC. Serial Interface All serial interface pins (CS/LD, SCK and SDI) have TTL input levels and are 5V tolerant. The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, activating the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 12-bit input code, ordered MSB-to-LSB, followed by 4 don't-care bits. Data can only be transferred to the device when the CS/LD signal is low. The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 3. The command (C3-C0) and address (A3-A0) assignments are shown in Table 3. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. While the minimum input word is 24-bits, it may optionally be extended to 32-bits to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 4 shows the 32-bit sequence. Power-Down Mode Either or both DAC channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, n. The 16-bit data word is ignored. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 3. The selected DAC is powered up as its voltage output is updated. If both DACs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power-up delay time is 700s (for VCC = 3V).
Table 3. Auxiliary DAC Commands
COMMAND* C3 0 0 0 0 0 1 A3 0 0 1 C2 0 0 0 0 1 1 A2 0 0 1 C1 0 0 1 1 0 1 A1 0 0 1 C0 0 1 0 1 0 1 A0 0 1 1 DAC A DAC B All DACs Write to Input Register n Update (Power-Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power-Up) n Power Down n No Operation
ADDRESS (n)*
*Command and address codes not shown are reserved and should not be used.
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18
CS/LD 2 7 13 14 17 D7
9002 F02
OPERATION
SCK 3 4 10 21 D3 D2 D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 16 20 22 C0 ADDRESS WORD A3 A2 A1 A0 D15 5 6 8 9 19 15 C1 C2 COMMAND WORD
1
SDI
C3
24-BIT INPUT WORD
Figure 2. Auxiliary DAC 24-Bit Load Sequence (Minimum Input Word)
CS/LD 6 7 13 14 17 D15 A2 ADDRESS WORD A1 A0 A3 X COMMAND WORD X C3 C2 C1 C0 8 9 10 11 12 16 15 X 18 D14 19 D13 20 D12 21 D11 22 D10 23 D9 24 D8 25 D7 DATA WORD 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
9002 F03
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
Figure 3. Auxiliary DAC 32-Bit Load Sequence
LTM9002
19
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LTM9002 APPLICATIONS INFORMATION
INPUT SPAN The LTM9002 is configured with a given input span and input impedance. With the amplifier gain and the ADC input network described above for LTM9002-AA, the full-scale input range of the driver circuit is 0.1VP-P. The recommended ADC input span is achieved by tying the SENSE pin to VDD. However, the ADC input span can be changed if required for the application. The resulting input span at the IN+/IN- pins is the ADC input span divided by the gain. The LTM9002 is intended to be driven through the IN+ and IN- pins. The DNC pins are used for test purposes and are not intended to be used in the application. These are test points within the ADC input filter network. However, care should be taken with these pins as they connect directly to the internal signal path. They should be soldered to an unconnected pad and should be well isolated. Input Impedance and Matching The input impedance of the amplifier is 50, 200 or 400 depending on the gain of the amplifier. In some applications the differential inputs may need to be terminated to a lower value impedance, e.g. 50, in order to provide an impedance match for the source. Several choices are available. One approach is to use a differential shunt resistor (Figure 4). Another approach is to employ a wide band transformer and shunt resistor (Figure 5). Both methods provide a wide band match. The termination resistor or the transformer must be placed close to the input pins in order to minimize the reflection due to input mismatch. Alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction.
Table 4. Differential Amplifier Input Termination Values
GAIN (dB) 8 14 20 26 ZIN/2 200 100 100 25 RT FIGURE 4 57 66.5 66.5 None RT FIGURE 5 400 None None None
25 IN- ZIN/2 500 25 IN+ ZIN/2 500 LTM9002
+ -
VIN RT
25
IN-
ZIN/2
500
9002 F04
Figure 4. Input Termination for Differential 50 Input Impedance Using Shunt Resistor
LTM9002 25 IN+ ZIN/2 500
1:4
+ -
VIN
**
RT
9002 F05
Figure 5. Input Termination for Differential 50 Input Impedance Using a Balun
Referring to Figure 6, amplifier inputs can be easily configured for single-ended input without a balun. The signal is fed to one of the inputs through a matching network while the other input is connected to the same matching network and a source resistor. Because the return ratios of the two feedback paths are equal, the two outputs have the same gain and thus symmetrical swing. In general, the single-ended input impedance and termination resistor RT are determined by the combination of RS, RG and RF , see Table 5.
Table 5. Single-Ended Amplifier Input Termination Values
GAIN (dB) 8 14 20 26 ZIN/2 200 100 100 25 RT FIGURE 6 59 68.5 66.5 150
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LTM9002 APPLICATIONS INFORMATION
RS 50 0.1F LTM9002 IN+ ZIN/2 500 RS/2 IN+ ZIN/2 LTM9002 500
+ -
VIN RT 0.1F
+ -
0.1F
VIN RT
RS 50 RT
IN-
ZIN/2
500
RS/2
9002 F06
IN-
ZIN/2
500
9002 F07
Figure 6. Input Termination for Differential 50 Input Impedance Using Shunt Resistor
Figure 7. Calculate Differential Gain
The amplifier is unconditionally stable, i.e. differential stability factor Kf > 1 and stability measure B1 > 0. However, the overall differential gain is affected by the source impedance in Figure 7: AV = | VOUT/VIN | = (500/(RS + ZIN/2) The noise performance of the amplifier also depends upon the source impedance and termination. For example, an input 1:4 transformer in Figure 5 improves the input noise figure by adding 6dB gain at the inputs. A trade-off between gain and noise is obvious when constant noise figure circle and constant gain circle are plotted within the input Smith Chart, based on which users can choose the optimal source impedance for a given gain and noise requirement. SENSE Pin Operation The internal voltage reference can be configured for two pin-selectable input ranges of 0.1V (50mV differential) or 0.5V (25mV differential) for LTM9002-AA. Tying the SENSE pin to VDD selects the higher range; tying the SENSE pin to 1.5V selects the lower range. For other versions of LTM9002, the input span is either 2VP-P divided by the gain or 1VP-P divided by the gain. An external reference can be used by applying its output directly or through a resistive divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. The SENSE pin is internally bypassed to ground with a 1F ceramic capacitor.
Input Range The input range can be set based on the application. The 0.1V input range (LTM9002-AA) will provide the best SNR performance while maintaining excellent SFDR. The lower input range will have slightly better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. Adjusting the Full-Scale Input Range To trim the full-scale range of one channel to match that of the other channel, first set the desired range for both channels by applying an external reference to SENSEA and SENSEB as shown in Figure 8. Set the DAC codes to approximately match the external reference voltage. Apply a full-scale voltage to the input of each channel. Read the output of both channels and adjust the setting for the DAC of one channel until the desired channel matching has been achieved. The adjustment range and step size depends on the resistor values chosen for or the source resistance of the external reference circuit. The external reference is connected to the SENSE pin which has 10k (1%) series impedance with the internal DAC voltage. For the circuit shown in Figure 8, the step size is 76V and the code representing 1V is 0xAAB (0.666748 decimal). In this example, the SENSE voltage trim range is from approximately 0.79V to 1.1V including offset and gain errors. Therefore, the effective input span can be trimmed from 39.6mV to 55.2mV with a step size of 3.8V. However, it is not recommended to
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LTM9002 APPLICATIONS INFORMATION
exceed 50mV. The internal 1000pF capacitor provides a corner frequency of 64kHz when used with the 2.5k external resistor. An additional 0.1F bypass capacitor may be required at the SENSE pin. The auxiliary DACs can be used without an external reference in applications that are not sensitive to close-in phase noise such as CCD imaging or oversampling of low amplitude signals. Without an external reference, the DAC step size will be 366V at the SENSE pin which results in a 18V step for the input span. In this case, the SENSE pin may be bypassed with 0.1F capacitor. The auxiliary DACs must be subsequently set each time the LTM9002 is powered up. Driving the Clock Inputs The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (Figure 9). The noise performance of the ADC can depend on the clock signal quality as much as on the analog input. Any noise present on the CLK signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.
LTM9002 RANGE SELECT 1.5V REFERENCE
REF
1.25V 2.5k REF BUFFER 1000pF
1V (OPEN CIRCUIT, 4k THEVENIN RESISTANCE)
SENSE 10k
10k DAC
SDI SCK CS/LD
9002 F08
Figure 8. Using an External Reference
CLEAN SUPPLY
4.7F
FERRITE BEAD
0.1F SINUSOIDAL CLOCK INPUT 0.1F 1k CLK 50 1k NC7SVU04 LTM9002
9002 F09
Figure 9. Sinusoidal Single-Ended CLK Driver
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LTM9002 APPLICATIONS INFORMATION
It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this time delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. Figure 10 and Figure 11 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full-scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 series resistor to act as both a lowpass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTM9002-AA is 125Msps and the LTM9002-LA is 65Msps. The lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM9002 is 1Msps.
4.7F
FERRITE BEAD
CLEAN SUPPLY
0.1F ETC1-1T CLK 100 LTM9002 DIFFERENTIAL CLOCK INPUT 5pF TO 30pF CLK LTM9002
9002 F11
9002 F10
0.1F
IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR
FERRITE BEAD VCM
Figure 10. CLK Driver Using an LVDS or PECL to CMOS Converter
Figure 11. LVDS or PECL CLK Driver Using a Transformer
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LTM9002 APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. DIGITAL OUTPUTS Table 6 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Note that OF is high when an overflow or underflow has occurred on either channel A or channel B.
Table 6. Output Codes vs Input Voltage, 100mV Input Span
IN+ - IN- (SENSE = VDD) 50mV OF 1 0 0 0 0 0 0 0 0 1 D13 - D0 (OFFSET BINARY) 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 D13 - D0 (2'S COMPLEMENT) 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000
DATA FROM LATCH OE OGND PREDRIVER LOGIC
Digital Output Modes Figure 12 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the ADC should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full-speed operation, the capacitive load should be kept under 10pF . Lower OVDD voltages will also help reduce interference from the digital outputs.
LTM9002 OVDD VDD VDD 0.1F OVDD 43 TYPICAL DATA OUTPUT 0.5V TO 3.6V
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Figure 12. Digital Output Buffer
0.000000V
-50mV
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LTM9002 APPLICATIONS INFORMATION
Data Format Using the MODE pin, the ADC parallel digital output can be selected for offset binary or 2's complement format. Note that MODE controls both channel A and channel B. Connecting MODE to GND or 1/3 VDD selects straight binary output format. Connecting MODE to 2/3 VDD or VDD selects 2's complement output format. An external resistive divider can be used to set the 1/3 VDD or 2/3 VDD logic values. Table 7 shows the logic states for the MODE pin.
Table 7. MODE Pin Function
MODE PIN 0 1/3VDD 2/3VDD VDD OUTPUT FORMAT Straight Binary Straight Binary 2's Complement 2's Complement CLOCK DUTY CYCLE STABILIZER Off On On Off
OVDD can be powered with any voltage from 500mV up to 3.6V, independent of VDD. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF The . data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full-speed operation. The output Hi-Z state is intended for use during test or initialization. Channels A and B have independent output enable pins (OEA, OEB.) Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting ADCSHDN to GND results in normal operation. Connecting ADCSHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and the ADC typically dissipates 1mW. When exiting sleep mode, it will take 700s to 1ms for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting ADCSHDN to VDD and OE to GND results in nap mode and the ADC typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state. Channels A and B have independent ADCSHDN pins (ADCSHDNA, ADCSHDNB.) Channel A is controlled by ADCSHDNA and OEA, and channel B is controlled by ADCSHDNB and OEB. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode. Digital Output Multiplexer The digital outputs of the ADC can be multiplexed onto a single data bus. The MUX pin is a digital input that swaps the two data busses. If MUX is high, channel A comes out on DAx; channel B comes out on DBx. If MUX is low,
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Overflow Bit For LTM9002-AA, when OF outputs a logic high the converter is either overranged or underranged on channel A or channel B. Note that both channels share a common OF pin. OF is disabled when channel A is in sleep or nap mode. For LTM9002-LA, OFA and OFB indicate either condition for the respective channel. Output Clock The LTM9002-AA has a delayed version of the CLKB input available as a digital output, CLKOUT. The falling edge of the CLKOUT pin can be used to latch the digital output data. CLKOUT is disabled when channel B is in sleep or nap mode. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same supply that powers the logic being driven. For example, if the converter drives a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.
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LTM9002 APPLICATIONS INFORMATION
the output busses are swapped and channel A comes out on DBx; channel B comes out on DAx. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together (see the Timing Diagram for the multiplexed mode.) The multiplexed data is available on either data bus - the unused data bus can be disabled with its OE pin. Supply Sequencing The VCC pin provides the supply to the amplifier and the auxiliary DAC while the VDD pin provides the supply to the ADC. The amplifier, ADC and the DAC are separate integrated circuits within the LTM9002; however, there are no supply sequencing considerations beyond standard practice. It is recommended that the amplifier, ADC and DAC all use the same low noise, 3.0V supply, but VCC may be operated from a different voltage level if desired. Both rails can operate from the same 3.0V linear regulator but place a ferrite bead between the VCC and VDD pins. Separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. Grounding and Bypassing The LTM9002 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9002 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The LTM9002 is internally bypassed with the ADC, (VDD) and amplifier and DAC (VCC) supplies returning to a common ground (GND). The digital output supply (OVDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is significant. The differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTM9002 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. Recommended Layout The high integration of the LTM9002 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9002, but can be connected on the PCB underneath the part to provide a common return path. * Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. * Separate analog and digital traces as much as possible, using vias to create high-frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the LTM9002. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The LTM9002 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp.
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26
LTM9002 PACKAGE DESCRIPTION
LGA Package 108-Lead (15mm x 11.25mm x 2.32mm)
(Reference LTC DWG # 05-08-1757 Rev O)
DETAIL A aaa Z 15 BSC X Y 2.22 - 2.42 13.97 BSC J H G MOLD CAP 11.25 BSC 0.27 - 0.37 1.95 - 2.05 // bbb Z Z 1.27 BSC D C B A PADS SEE NOTES 3 DETAIL B 6.985 5.715 4.445 3.175 1.905 0.635 0.000 0.635 1.905 3.175 4.445 5.715 6.985 0.630 0.025 SQ. 108x eee S X Y 12 11 10 9 8 7 6 5 4 3 2 1 DIA (0.635) PAD 1 SUBSTRATE 10.16 BSC F E
0.22 x 45 CHAMFER
PAD 1 CORNER 4 aaa Z
DETAIL B
PACKAGE TOP VIEW
PACKAGE BOTTOM VIEW
5.080 3.810 2.540 1.270 0.000 1.270 2.540 3.810 DETAIL A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
COMPONENT PIN "A1"
LTMXXXXXX Module
5.080
SUGGESTED PCB LAYOUT TOP VIEW
TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION
LGA 108 0707 REV O
5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 108 SYMBOL TOLERANCE 0.15 aaa 0.10 bbb 0.05 eee
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM9002 RELATED PARTS
PART NUMBER LT1994 LTC2205 LTC2206 LTC2207 LTC2208 LTC2240-12 LTC2241-12 LTC2242-12 LTC2248 LTC2249 LTC2254 LTC2255 LTC2282 LTC2283 LTC2284 LTC2285 LTC2293 LTC2294 LTC2295 LTC2296 LTC2297 LTC2298 LTC2299 LT5557 LT5575 LTC6400-8/LTC6400-14/ LTC6400-20/LTC6400-26 LTC6401-8/LTC6401-14/ LTC6401-20/LTC6401-26 DESCRIPTION Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs 12-Bit, 210Msps, 2.5V ADC, LVDS Outputs 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 14-Bit, 65Msps ADC 14-Bit, 80Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps ADC Dual 12-Bit, 105Msps ADC Dual 12-Bit, 125Msps ADC Dual 14-Bit, 105Msps ADC Dual 14-Bit, 125Msps ADC Dual 12-Bit, 65Msps ADC Dual 12-Bit, 80Msps ADC Dual 14-Bit, 10Msps ADC Dual 14-Bit, 25Msps ADC Dual 14-Bit, 40Msps ADC Dual 14-Bit, 65Msps ADC Dual 14-Bit, 80Msps ADC 400MHz to 3.8GHz 3.3V High Linearity Downconverting RF Mixer 800MHz to 2.7GHz High Linearity Direct Conversion Quadrature Demodulator Low Noise, Low Distortion Differential Amplifier for 300MHz IF Fixed Gain of 8dB, 14dB, 20dB or 26dB , Low Noise, Low Distortion Differential Amplifier for 140MHz IF Fixed Gain of 8dB, 14dB, 20dB or 26dB , COMMENTS Low Distortion: -94dBc at 1MHz 530mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 445mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN 585mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN 745mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN 210mW, 74dB SNR, 5mm x 5mm QFN 230mW, 73dB SNR, 5mm x 5mm QFN 320mW, 72.5dB SNR, 88dB SFDR, 5mm x 5mm QFN 395mW, 72.4dB SNR, 88dB SFDR, 5mm x 5mm QFN 540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN 790mW, 70.2dB SNR, 88dB SFDR, 64-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN 790mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN 410mW, 71dB SNR, 9mm x 9mm QFN 445mW, 70.6dB SNR, 9mm x 9mm QFN 120mW, 74.4dB SNR, 9mm x 9mm QFN 150mW, 74dB SNR, 9mm x 9mm QFN 240mW, 74dB SNR, 9mm x 9mm QFN 410mW, 74dB SNR, 9mm x 9mm QFN 445mW, 73dB SNR, 9mm x 9mm QFN 24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO Ports, 3.3V Supply 60dBm IIP2 at 1.9GHz, NF = 12.7dB, Low DC Offsets 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
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28 Linear Technology Corporation
(408) 432-1900
LT 0509 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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